Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. A DRAM memory cell has only one transistor and one capacitor, so it provides a high degree of integration. Because DRAM requires constant refreshing, its power consumption and slow speed limit its use mainly for computer main memories. The SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as an adequate power is supplied. SRAM can operate at a higher speed with lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of an SRAM cell is a six transistor (6-T) cell that comprises six metal-oxide-semiconductor (MOS) transistors. As illustrated in FIG. 1, a 6-T SRAM cell 100 comprises two identical cross-coupled inverters 102 and 104 that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between a power supply and a ground potential.
Referring to FIG. 1, each inverter 102 or 104 comprises an NMOS pull-down transistor 115 or 125 and a PMOS pull-up transistor 110 or 120, respectively. The inverters' outputs serve as two storage nodes, Q and QB. When one of the storage nodes is pulled to low voltage, the other storage node is pulled to high voltage forming a complimentary pair. A complementary bit line pair BL and BLB is coupled to the storage nodes Q and QB via a pair of pass-gate transistors 130 and 135, respectively. The gates of the pass-gate transistors 130 and 135 are connected to a word line WL.
When the word line voltage is switched to a system high voltage, the pass-gate transistors 130 and 135 are turned on to allow the storage nodes Q and QB to be accessible by the bit line pair BL and BLB, respectively. When the word line voltage is switched to a system low voltage, the pass-gate transistors 130 and 135 are turned off and the storage nodes Q and QB are essentially isolated from the bit line pair BL and BLB and the state of the storage nodes Q and QB is maintained almost indefinitely. The cross-coupled inverters 102 and 104 continue to reinforce each other as long as they are isolated from the outside world.
A write operation is performed by applying the state to be written in to the bit line BL and the bit line BLB. For example, for writing a state “1”, a system low voltage is applied on the bit line BL, whereas a system high voltage e.g., supply voltage (Vdd), is applied on the bit line BLB. The word line WL is then asserted and the value that is to be stored is latched in overriding the relatively weak transistors of the cross-coupled inverters 102 and 104. When system low voltage is applied on the bit line BL, the PMOS pull-up transistor 120 is overpowered and drives the output of the inverter 102 high, latching “1” in the node QB of the cell.
Prior to the starting time of the read operation, pass-gate transistors 130 and 135 are off since the word line voltage is low, for example, at 0V. The read operation is performed by pre-charging both bit lines BL and BLB to supply voltage Vdd, and then raising the voltage of gates of the pass-gate transistors 130 and 135 to high (through the word line WL). The state of the cell 100 (potential on storage nodes Q and QB) changes the voltage of one of the bit line pair BL and BLB. For example, assuming the previously stored data is 1, which means that storage node Q is at a low voltage and storage node QB is at a high voltage, when word line WL is activated, pass-gate transistors 130 and 135 are turned on. The data “0” stored in the storage node Q will cause the discharge of bit line BL to “0” through pass-gate transistor 130. A sense-amplifier circuit detects a voltage difference between the bit line pair BL and BLB identifying the stored state.
As memory begins to dominate the chip area in high performance applications, SRAM has become the focus of technology scaling. Traditionally, SRAM cell size has scaled with technology scaling. However, at aggressively scaled technologies, variability has increased dramatically, challenging traditional methods to scaling. SRAM devices are most susceptible to both process induced variations as well as intrinsic threshold voltage variations (such as due to random dopant fluctuations) because SRAM devices are fabricated using minimum gate length and gate width devices. Variability is most pronounced in SRAMs because cell operation must be satisfactory for each individual cell with no averaging across multiple cells as in logic.
Consequently, as SRAMs are scaled, sufficient static noise margin (SNM) is difficult to achieve due to both increased variation and noise. In particular, mismatch between reflected SNMs of the two halves of the SRAM cell is enhanced due to aggressive ground rules and dopant fluctuations. Further, at minimum gate length and gate width transistors, the SNM is further degraded due to distortion of the inverter transfer characteristics. Hence, cell stability which determines minimum array operating voltage and yield has thus increasingly become difficult to achieve.
To function properly, the SRAM cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell or when holding data, the cell current generated (as the pass-gate transistor turns ‘on’) must not flip the voltage level at the internal storage nodes Q and QB.
One of the stability problems of an SRAM cell array is associated with half select operating mode. In a half select operating mode, a row of the SRAM array is selected while a column is not, i.e., the word line WL is ON and one or more of the bit line pairs BL and BLB is clamped to a supply voltage (Vdd). During a write operation on a cell, both the row and column of the array are selected. This is illustrated in FIG. 2, which illustrates an SRAM cell array comprising SRAM cells cell00, cell01, cell02, cell10, cell11, cell12, cell20, cell21, and cell22. Each cell is accessed with a corresponding bit line pair (BL0, BL1, or BL2) and a corresponding word line pair (WL0, WL1, or WL2). The bit line pairs BL and BLB are illustrated as (1,0) if the column is selected for writing or (1,1) if the column is not selected. The corresponding word lines WL (WL0, WL1, and WL2) controlled by the word line drivers are turned to a system high voltage (ON) or a system low voltage (OFF). Hence, during the write operation illustrated in FIG. 2, the cell00 is selected, whereas cell01 and cell02 are not selected.
However, during a write operation of the cell00, all the pass-gate transistors of cells in the same row (cell01 and cell02) are turned ON exposing the storage nodes in these adjacent cells. With the pass-gate transistors turned ON for that selected word line, the cross-coupled cell inverters are coupled to the corresponding bit line pairs, partially selecting the cells (half selected) on that word line. Unfortunately, imbalances within the cell can upset half selected cells, or at the very least, become meta-stable at normal design voltages. Thus, due to half select disturbance, cells adjacent to the cell being written may be accidentally disturbed even though the columns for these adjacent cells are OFF. Hence, what is needed are circuits and methods of overcoming half select disturbance for an SRAM cell array.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.